This invention relates generally to the area of system interconnect technology.
As CPU speeds approach the multi-gigahertz range, system designers increasingly focus on system interconnect as the primary bottleneck at the chip-to-chip, board-to-board, backplane and box-to-box levels. System interconnect has evolved from utilizing parallel I/O technology with source-synchronous clocking or system-synchronous clocking to multi-gigabit serial I/O with clock-data recovery (“CDR”). Channel aggregation bonds individual serial I/O lanes to create a multi-lane link, transcending the bandwidth limitations of single transceiver channels and providing the high bandwidth required by next generation serial protocols such as 40/100 Gigabit Ethernet and PCI Express Gen 3. However, various communication protocols have different functional requirements. At the same time, there is an increasing need for system designers to have flexibility in designing systems to work with one particular protocol versus another. Moreover, protocols continue to evolve, so there is a need for transceivers that can be reconfigured to meet the needs of future potential variations in high speed communication protocols. Such protocols may change during the product life of an integrated circuit (“IC”); therefore there is a need for a configurable transceiver design flexible enough to potentially accommodate such changes.
Deskew represents one of the processing stages in a high speed transceiver. However, different protocols have different deskew techniques. For example, many protocols rely on deskew characters to align data across multiple lanes. The characters and the insertion frequency of characters may vary depending on the protocol. Moreover, the preferred buffer depth might vary depending on the protocol. Also, depending on the application and/or protocol, it might be necessary to take into account one or both of dynamic and static skew, separately or in combination. Furthermore, there may be a need for flexibility in controlling a transceiver from either user-defined logic in the core and/or from configurable control circuitry in the transceiver itself. In addition, it might be required that deskew processing occur either before or after other processing (e.g. clock compensation processing) depending upon the protocol.
For these reasons, a configurable transceiver with configurable deskew circuitry that can be re-configured to adapt to different deskew requirements and user control requirements is needed.